• System Controller

• DMA Controller

• Programmable Interrupt Controller

• Programmable Interval Timer

• LCD controller

• Advanced Vectored Interrupt controller

The system controller core connects the system CPU to system memory, PCI bus, IO ports and external communication links. While the CPU’s task in the system is to process data, the system controller’s main function is to coordinate data movement in the system. The system controller contains all the major functional modules required for most System-on-Chip (SOC) application. The entire system controller function can be easily integrated into a single ASIC or PLD.

The system controller contains SDRAM controller, PCI bridge, DMA function, UART, bus arbiter and system control registers. Internal to the system controller, these modules are connected to each other directly to achieve high performance and concurrent data movement between various source and data destinations. Since each module is implemented as synthesizable HDL code, each function can be re-configured or modified as required. All modules are designed with a common interface. The connectivity between the modules can be modified easily to meet different system requirements. Modules not needed for specific application can be removed from the core to minimize die size and gate count.

Different system controllers are available for different CPU types. Currently the CPU supported are: ARM CPU, MIPS CPU with SysAD bus and EC Interface, PowerPC 603, 604, 740, 750, MPC8260, 860, Hitachi SH2, SH3 and SH4. The CPU bus can be 32-bit or 64-bit wide depending on the CPU type. Burst data transfer is supported by the system controller.

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The core is provided with the generic processor bus interface on the system side enabling the core to be used in a variety of applications including SoC applications. The core's simple and configurable architecture is independent of implementation tools and, most importantly, target technologies. DMA Controller core is a cost-effective, end-to-end solution that allows the licensees to easily migrate to FPGA, Gate array and Standard cell technologies optimally.

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Programmable Interrupt Controller

• MCS-80/85 and 8088/8086 processor modes
• Fully nested mode and special fully nested mode
• Special mask mode
• Buffered mode
• Pool command mode
• Cascade mode with master or slave se-lection
• Automatic end-of-interrupt mode
• Specific and non-specific end-of-interrupt commands
• Automatic and Specific Rotation
• Edge and level triggered interrupt input modes
• Reading of interrupt request register (IIR) and in-service register (ISR) through data bus.
• Writing and reading of interrupt mask register (IMR) through data bus

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Programmable Interval Timer

• Real time clock
• Even counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
• Complex motor controller

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LCD controller

Advanced Vectored Interrupt controller