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PCI Bus

PCI Express Controllers
   

PCI-X Host Bridge

The 64-bit PCI-X host bridge core is optimized to operate in both PCI mode and PCI-X mode. The user interface is a highly efficient and flexible user interface which provides for easy integration with the CPU and other user logic. The core automatically switch between PCI and PCI-X protocol based on the system environment. It supports both PCI version 2.3 and PCI-X version 1.0b.

Features

  • Fully supports PCI 2.3 and PCI-X protocol 1.0b.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.
  • Efficient user interface for different types of user devices.
  • User interface and PCI interface runs at different clock speed.
  • User interface independent of PCI or PCI-X configuration.
  • Include data buffer and synchronization logic to bridge the two clock domains.
  • Automatic detection of PCI and PCI-X bus systems.
  • Combined bus master and target functions including split completion.
  • Host bridge function to initiate configuration access with internal CONFIG_ADDR and CONFIG_DATA registers.
  • Supports Zero wait state and user inserted wait state burst data transfer.
  • Dual write buffer in each direction to support write data posting.
  • Automatic handling of configuration register read/write access.
  • Parity generation and parity error detection.
  • Includes all PCI and PCI-X specific configuration registers.
  • Supports high speed bus request and bus parking.

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PCI-X Master/Target

The 64-bit PCI-X master/target core is optimized to operate in both PCI mode and PCI-X mode. The back-end interface is a highly efficient and flexible back-end bus which provides for easy integration with other user logic. The core automatically switch between PCI and PCI-X protocol based on the system environment. It supports both PCI version 2.2 and PCI-X version 1.0.

Features

  • Fully supports PCI and PCI-X protocol.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.
  • Efficient user interface for different types of user devices.
  • User interface and PCI interface runs at different clock speed.
  • Include data buffer and synchronization logic to bridge the two clock domains.
  • Automatic detection of PCI and PCI-X bus systems.
  • Combined bus master and target functions.
    • Master function
    • Initiate PCI memory and IO read/write.
    • Automatic transfer restart on target retry and disconnect.
    • Target function
    • Memory or IO read/write.
    • Configuration read/write.
    • Split transaction.
  • Supports Zero wait state and user inserted wait state burst data transfer.
  • Dual write buffer in each direction to support write data posting.
  • Automatic handling of configuration register read/write access.
  • Parity generation and parity error detection.
  • Includes all PCI specific configuration registers.
  • Supports high speed bus request and bus parking.

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PCI Master/Target
PCI bus Master/target contains both the functions to initiate PCI bus access as well as to respond to PCI access. The design employs a very user-friendly back-end interface to allow different user logics to communicate with the PCI bus. DMA controller, FIFOs and communication processors can be easily connected to the PCI bus master/target. Target function and configuration registers are included in the design.
  • 64-bit and 32-bit bus sizes are supported
  • Mini-PCI, Cardbus, Compact PCI and Power Management supports.
  • Options for asynchronous back-end use interface.

Features

  • Compliant with PCI specification 2.2/2.3/3.0 protocol.
  • Designed for ASIC and FPGA implementations in various system environments.
  • Combines bus master and bus target functions in one core.
  • Supports burst transfer to maximize memory bandwidth.
  • Zero wait state PCI data transfer. Up to 133Mbyte/sec at 33Mhz and 266Mbyte/sec at 66Mhz.
  • Supports target retry, disconnect and target abort.
  • Automatic transfer restart on target retry and disconnect.
  • Concurrent bus master and target function.
  • Write buffer for target write data posting to increase PCI bus performance.
  • Responds to standard PCI configuration access.
  • Supports all PCI specific configuration registers.
  • User controlled base address register sizing and mapping.
  • Retry counter to limit bus access to non-responsive target device.
  • PCI status directly available to user logic for interrupt generation.
  • Option for integrated DMA controller.
  • Option for AMBA AHB and other CPU interface.

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PCI Target
PCI bus target contains functions as a target to all PCI bus accesses. A microprocessor style back-end bus interface allow different user logic to be connected to the target. It sustains zero wait state data transfer indefinitely without the use of any FIFOs. Many different features of the PCI, such as retry, disconnect, and bus abort, are supported.
  • 64-bit and 32-bit bus sizes are supported.
  • Compact design. Basic design requires less than 3000 gates.
  • Mini-PCI, Cardbus, Compact PCI and Power Management supports.
  • Options for asynchronous back-end use interface.

Features

  • Fully supports PCI specification 2.1 and 2.2 protocol.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.
  • Efficient back-end interface for different types of user devices.
  • Supports compact PCI, Cardbus, Mini-PCI and Power Management.
  • Supports zero wait state data burst transfer to maximize memory bandwidth.
  • Zero wait state and user inserted wait state burst data transfer.
  • Dual write buffer supports write data posting.
  • User controlled burst and non-burst data transfer.
  • Multiple address mapping to memory and IO address spaces.
  • Automatic handling of configuration register read/write access.
  • Supports back-end initiated target retry, disconnect and abort.
  • Supports delayed data transaction initiated by user logic.
  • Parity generation and parity error detection.
  • Includes all PCI specific configuration registers.

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PCI Host Bridge
The PCI host bridge allows different types of host CPUs to access the PCI bus resources and to configure the PCI bus under software control. Many design options are possible on the host bridge.
  • 64-bit and 32-bit bus sizes are supported.
  • Synchronous or Asynchronous clock between CPU host bus and PCI bus.

Features

  • Fully supports PCI specification 2.1 and 2.2 protocol.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.
  • Efficient back-end interface for different types of user devices.
  • Host bridge design includes bus master, bus target and central system functions.
  • Generates standard PCI type 0 and type 1 configuration accesses.
  • Combined bus master and target functions.
    • Master function
    • Initiate PCI memory and IO read/write.
    • Automatic transfer restart on target retry and disconnect
    • Target function
    • Memory or IO read/write
    • Configuration read/write
    • Support for back-end initiated target retry, disconnect and abort.
  • Supports Zero wait state and user inserted wait state burst data transfer.
  • Dual write buffer supports write data posting.
  • User controlled burst and non-burst data transfer.
  • Automatic handling of configuration register read/write access.
  • Supports user initiated target retry, disconnect, abort and delayed transaction.
  • Parity generation and parity error detection.
  • Includes all PCI specific configuration registers.
  • Supports high speed bus request and bus parking.
  • Optional PCI bus arbiter with fix, rotating, and custom priority.

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PCI-PCI Bridge

The PCI-to-PCI Bridge connects between a primary PCI bus and a secondary PCI bus. Data access is allowed to flow between the two buses in both directions.

Features

  • Fully supports PCI bus specification 2.2 and PCI bridge specification 1.1.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.
  • Independent asynchronous PCI clocks on primary and secondary bus.
  • Convert bus transactions between primary bus and secondary bus.
  • Combined bus master and target functions on both primary bus and secondary bus.
    • Master function
    • Initiate PCI memory and IO read/write
    • Automatic transfer restart on target retry and disconnect
    • Initiate type 0 and type 1 configuration access on secondary bus
    • Target function
    • Memory or IO read/write
    • Receives type 0 and type 1 configuration access on primary bus
    • Posted memory write transaction and delay transaction on all other transaction types
  • Dual write buffer on each direction supports posted memory write.
  • Supports prefetchable and non-prefetchable memory read.
  • Delay transaction processes IO read/write, configuration read/write and memory read transactions.
  • Supports target retry, disconnect, master abort and target abort terminations.
  • Parity generation and parity error detection.
  • Includes all PCI-PCI bridge specific configuration registers.
  • Supports high speed bus request and bus parking.
  • Optional PCI bus arbiter with fix, rotating, and custom priority.

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PCI-ISA Bridge

The PCI-to-ISA bridge allows PCI masters to access ISA slave devices. It maps a specific address space in the PCI bus to the ISA bus space and convert PCI transactions to ISA transactions.

Features

  • Compliant with PCI bus specification 2.1 and 2.2.
  • Convert PCI transaction to ISA bus transaction.
  • Function as PCI target on PCI bus.
  • Function as ISA master on ISA bus.
  • Map PCI address space to ISA address space through Base Address Register.
  • Supports 16-bit and 8-bit data transfer, memory and IO transfers on ISA bus.
  • ISA bus operates on one-fourth the frequency of the PCI clock.
  • Performs multiple ISA operations to transfer each 32-bit PCI word.
  • Write buffer to speed up PCI-to-ISA write transfer.
  • Support ISA devices with different speed by using NOWS# and CHRDY signals.
  • Parity generation and parity error detection on PCI bus.
  • Includes all PCI specific configuration registers.
  • Fully synchronous design, no gated clock or transparent latch. All flip-flops are rising edge trigger.

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PCI Bus Arbiter

The PCI bus arbiter arbitrates between multiple bus masters on the PCI bus. Rotating priority, fixed priority and bus parking are implemented. The bus arbiter also supports bus latency time-out and observes bus grant turn-around-time requirements.

Features

  • Compliant with PCI bus specification 2.1 to 3.0
  • Designed for ASIC and PLD implementations in various system environments.
  • Supports two to eight bus masters.
  • Run time selection between rotating priority or fix priority scheme.
  • Bus parking.
  • Single cycle request-to-grant turn around time.
  • Quiet cycle during master switch.
  • Master time-out.

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PCI Express End Point Controller

PCI Express End Point Controller is a highly flexible and configurable design targeted for end-point implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint.

The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. The solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications.

Features

  • Compliant to PCI Express base specification version 2.0* (5.0 Gbps) and fully compliant for PCI Express Specification 1.1 (2.5 Gbps) for Gen1 requirements
  • Implements transaction, data link and physical layers
  • Supports multiple lanes: x1, x2, x4, x8 or x16
  • Architected for high link utilization and low latency
  • Efficient receive and transmit-retry buffering scheme
  • Completely handles PCI-Express ordering rules
  • Implements flow control logic for both directions
  • Packet oriented user logic interface
  • Supports PIPE based PHY architecture
  • Optional DMA controller on the user logic side
  • Flexible lane ordering and support for lane reversal

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PCI Express Root Complex

PCI Express Root Complex controller is a highly flexible and configurable design targeted for root-complex implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint.

This is part of PCIExpress family of IP solutions, which includes End Point, Root Complex and Advanced Switching designs.

The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. The solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications.

Features

  • Compliant to PCI Express base specification version 2.0* (5.0 Gbps) and fully compliant for PCI Express Specification 1.1 (2.5 Gbps) for Gen1 requirements
  • Implements transaction, data link and physical layers
  • Supports multiple lanes: x1, x2, x4, x8 or x16
  • Architected for high link utilization and low latency
  • Efficient receive and transmit-retry buffering scheme
  • Completely handles PCI-Express ordering rules
  • Implements flow control logic for both directions
  • Packet oriented user logic interface
  • Supports PIPE based PHY architecture
  • Optional DMA controller on the user logic side
  • Flexible lane ordering and support for lane reversal

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PCI Express Switch Controller

PCI Express Switch controller is a highly flexible and configurable design targeted for switch implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint.

This is part of PCIExpress family of IP solutions, which includes End Point, Root Complex, Hybrid, Switch port Controller, Switch and Advanced Switching designs. This comes in 2 flavors, Upstream Switch port and Downstream Switch Port. These flavors allow a Transparent or Non-Transparent PCIe Switch implementation with implementation specific port and Data path arbitration schemes.

The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. The solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications.

Features

  • Compliant to PCI Express base specification version 2.0* (5.0 Gbps) and fully compliant for PCI Express Specification 1.1 (2.5 Gbps) for Gen1 requirements
  • Implements transaction, data link and physical layers
  • Supports multiple lanes: x1, x2, x4, x8 or x16
  • Architected for high link utilization and low latency
  • Completely handles PCI-Express ordering rules
  • Implements flow control logic for both directions
  • Optional packet buffer and scheduler modules
  • Packet oriented user logic interface
  • Supports configurable number of downstream ports
  • Supports parallel address decoding
  • Supports Type1 configuration space
  • Allows access to port configuration space from line and GPI
  • Supports Type0/1 configuration conversions
  • Handling of UR for both upstream and downstream traffic
  • Flexible lane ordering and
  • support for lane reversal

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PCI Express Switch

A PCI Express switch provides fan-out capability and enables a series of connectors for add-in, high performance I/Os. PCIe switches allow limited north bridge resources to be distributed to multiple I/O end points and enable efficient use of available bandwidth

The PCI Express Switch solution is a complete full functional PCI Express switch consisting of the switch core and the switch port controllers and implements the entire switch functionality like packet routing, interrupt, configuration access, power management and error reporting functions.

Features

  • Compliant with PCI Express Base 1.1 or 2.0 Specifications
  • Complete solution with upstream /downstream switch ports and the switch interconnect
  • Highly configurable: Support for x1, x4, x8, x16-lane implementations
  • 5Gbps data rate per lane in Gen 2 mode
  • Internal data path width: 64 or 128 bits
  • TLP data payload size from 128 B to 4 KB
  • Ability to configure the features of each switch port independently
  • Non blocking architecture for high link utilization and low latency
  • Parallel address decoding for all egress ports
  • Support for integrated Endpoints within the switch
  • Up to 8 virtual channels
  • Efficient buffering scheme for Retry buffer and receive buffer
  • Completely handles PCI Express ordering rules and flow control
  • INTX, MSI interrupt support
  • Round Robin, Strict Priority and WRR support for VC arbitration for Port Arbitration
  • Option to connect an integrated/embedded Endpoint to any Downstream Port without PCIe Link
  • Unsupported request and unexpected completion handling for both upstream and downstream traffic
  • Lane ordering and reversal
  • Isochronous transfers supported

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PCIe-AXI Bridge

The PCI Express*-AMBA AXI Bridge (PCIe-AXI Bridge) is a highly flexible and configurable IP with a PCI Express interface on one side and an AMBA AXI interface on the system side. The Bridge has been architectured to interface with a PCI Express controller used as an end-point or root-complex type devices. The PCIe-AXI BRIDGE uses high speed multi-channel DMA controllers to match the bandwidth requirements of the PCIe Gen2 solution.

The PCI Express-AXI Bridge is a simple, configurable and layered architecture, independent of applications, implementation tools or target technology. The controller architecture is carefully tailored to optimize latency, power consumption, and silicon footprint, making it ideal for cost and performance sensitive applications. The PCIe-AXI BRIDGE solution provides highly scalable bandwidth through a configurable data path width and clock frequency.

Features

  • PCI Express to AMBA AXI Bridge complaint to PCI Express 2.0 and 1.1 Base specification
  • AMBA AXI protocol 1.0 compliant
  • AXI PIO operation with configurable number of AXI Slaves supported
  • PCIE PIO operation with configurable number of AXI Masters supported
  • Multi-channel DMA transfers supported
  • Register based and descriptor based modes of DMA supported
  • Read and write DMAs supported
  • Interrupt generation to both AXI and PCI Express supported
  • Vendor defined messages supported
  • Software configurable address mapping between PCI Express and AXI systems
  • Exhaustive Control, Status and Debug registers
  • CSR registers optional access through APB
  • PCI Express Features
    • Maximum link width: x16 link
    • Max payload size of 4096B
    • Up to 8 Virtual Channels supported
    • Up to 8 functions supported
    • Data path width: 32, 64 and 128-bits
    • Efficient Receive VC buffer implementation
    • Configurable Receive VC buffer size
    • PCI Express ordering rules implemented
    • INTx, MSI and MSI-X interrupt mechanisms

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PCI Express AMBA-AHB Bridge

The PCI Express*-AMBA AHB Bridge is a highly flexible and configurable IP with the PCI Express interface on one side and an AMBA sub system on the other side. The Bridge has been architectured to interface with a PCI Express controller used as an end-point or root-complex devices. The IP uses high speed multi-channel DMA controllers to match the bandwidth requirements of a PCIe Gen2 solution. The design supports AHB PIO, PCI Express PIO, and Write DMA and read DMA types of transfers.

Features

  • Gen2 PCI Express to AMBA AHB Bridge for PCI Express Base 2.0* (5.0 Gbps) requirements and fully compliant bridge for PCI Express r1.1 (2.5 Gbps) specification
  • Compliant to PIPE specification v1.0
  • Maximum link width: x16 link
  • Max payload size of 4096B
  • Up to 8 Virtual Channels supported
  • Up to 8 functions supported
  • Data path width: 32, 64 and 128-bits
  • INTx, MSI and MSI-X interrupt mechanisms
  • Efficient Receive VC buffer implementation
  • Configurable Receive VC buffer size
  • PCI Express ordering rules implemented
  • Interrupt generation to both AMBA and PCI Express supported
  • Vendor defined messages supported
  • Software configurable address mapping between PCI Express and AMBA systems
  • Exhaustive Control, Status and Debug registers
  • CSR registers optional access through APB
  • AMBA AHB 2.0 compliant
  • Full and Lite mode operation supported
  • AMBA PIO operation with configurable number of AHB Slaves supported
  • PCIE PIO operation with configurable number of AHB Masters supported
  • Multi-channel DMA transfers supported
  • Register based and descriptor based modes of DMA supported
  • Optional configurable number of Read and write DMAs supported

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